The present invention relates, in general, to contact etch processes and, more particularly, to sloped contact etches in multilayer metal systems.
Semiconductor integrated circuits comprise a plurality of circuits and devices which are interconnected by one or more patterned metal layers, also called interconnect layers, formed on a top surface of the integrated circuits. The interconnect layers are separated from each other and the circuit by interlayer dielectric films. As device dimensions approach the submicron level, one limiting factor for further reduction in size is area required for device interconnections. A major component of interconnect area is the size of contact windows, or vias, which are selectively
etched in the interlayer dielectric. Contact windows are etched to expose portions of the underlying circuit or a lower interconnect layer. An upper interconnect layer is formed on top of the interlayer dielectric and in contact with the underlying circuit or the lower interconnect layer through the contact window.
Etch processes used to form contact windows can be classified generally as wet or dry. Wet etch processes are usually isotropic and thus undercut the masking layer somewhat while vertically etching the dielectric layer. Dry etch processes are highly anisotropic and create vertical sidewalls with the top and bottom of the contact window having substantially the same dimensions. Wet etch processes are undesirable for submicron geometries because the undercut significantly increases the lateral area required for the contact window. Though dry etch processes are compatible with the submicron dimensions of contact windows, the vertical sidewalls result in a via which is difficult to fill when the upper interconnect layer is deposited.
Interconnect layers deposited by conventional metal deposition methods become less reliable as the size of the contact window becomes comparable to the thickness of the interlayer dielectric. Deposited metal does not conform to the contours of the contact window especially at sharp corners, resulting in thin metal and voids when contact windows are small. This is a particular problem when dry etch processes are used and sidewalls of the via are vertical. In these cases, which are common in submicron geometry devices, the sidewalls of the via must be sloped to improve metal step coverage. One such sloped contact etch process is described in U.S. Pat. No. 4,698,128 issued to Berglund et al and assigned to the same assignee as the present invention. The Berglund et al method was a modified dry etch process which creates a stepwise sloped sidewall of the contact window. This process, however, required a time consuming dry etch cycle, and so was not desirable for via etches in thick dielectric layers. Another method is discussed in U.S. Pat. No. 4,352,724 issued to Sugishima et al. The Sugishima et al method used an isotropic etch to form a top portion of the via, followed by a single dry etch to form a bottom portion of the via. Though the Sugishima et al process was suitably fast for thick dielectric etches, a corner was formed at an interface of the isotropically etched region and the dry etch region. This corner created a metal step coverage problem similar to that created when no sloped etch process was used. Also, the anisotropic etch used by Sugishima et al caused a polymer veil to form inside the via which was difficult to remove. The polymer veil would either remain in the via, which caused poor metal contact, or break away in subsequent processing and redeposit on other portions of the semiconductor device, which created defects on the other portions of the device.
Accordingly, it is an object of the present invention to provide a method for producing a sloped contact via which results in improved metal step coverage.
It is a further object of the present invention to provide a method for producing a sloped contact window in a thick dielectric layer with a short processing time.
It is a further object of the present invention to provide a method for producing a sloped contact window in a thick dielectric layer which eliminates polymer veils.
It is a still further object of the present invention to provide a method for producing a sloped contact window in a thick dielectric layer with improved metal step coverage of via sidewalls resulting in improved reliability.